Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

WITH increasing demand for ever smaller, portable, energy-efficient and high-performance electronic systems, scaling of CMOS technology continues. As CMOS scaling approaches physical limits, continued innovation in materials, manufacturing processes, device structures and design paradigms have been necessary. High-k oxide and metal-gate stack were introduced to address oxide leakage; thin body undoped channels, and multiple-gate structures were introduced to mitigate subthreshold leakage; restricted design rules were introduced to improve layout efficiency; yet CMOS technology continues to be challenged in the areas of device aging and reliability. While CMOS is expected to be the dominant semiconductor technology for the foreseeable future, for reasons that are both technological and financial, alternatives to CMOS technology are attracting attention from the researchers. A large variety of post-CMOS devices have been proposed, including carbon nanotube (CNT) field-effect transistors (CNT-FETs), graphene filed-effect transistors (GFETs), tunnel transistors, graphene nanoribbon tunnel field-effect transistors (GNR-TFET), quantum-dots, and single-electron devices (SET). Newer memory technologies such as resistive random-access memory (Re-RAM) have already become commercial, while memristors, Spin Transfer Torque Random Access Memory (STT-RAM) technologies are progressing at a rapid pace. In parallel with this evolution of the device landscape, computing architectures as well have seen a relevant evolution, pushed by the rise of multi/many-core processors and the stringent request for energy efficiency.Multi-core processors are now widely used across many application domains spanning from embedded to high performance computing (HPC) and specific multicore architectures like GPGPU and network processors became dominant in their market segments. The complexity of the memory hierarchy is increased, requiring novel designs such as Non-Uniform Memory Access (NUMA). Communication among the different (heterogeneous) cores of the processor and fostered the evolution of several Network onChip (NoC) architectures. Indeed, to be able to exploit the benefits of these powerful architectures innovative resourcemanagement policies are necessary, solutions able to take into account not only the classical aspects of power and performance, but also reliability, which—for the above-mentioned reasons, has become a key issue not only in critical application environments. More precisely, testing and managing reliability, availability and serviceability (RAS) are the challenges that have become crucial for the success of nanoelectronic circuits and systems. This is the driving motivation for this special section of the IEEE Transactions on Computers and IEEE Transactions onNanotechnology. The relevance of this topic and the timeliness of this joint Special Section have elicited great response from the research community. This special section attracted 60 papers, involving 300 reviews by more than 150 expert reviewers with careful attention to avoid any conflict of interest. Consequently, this special section, the result of a large collective effort, is one that we are happy to introduce. The review process resulted in selection of three papers focused on the nanotechnology that are being published in the Transactions on Nanotechnology. The joint special section of the Transactions on Computers includes 10 additional papers, focused on architectural and system-level aspects of the design of reliable systems, working at different levels of abstraction. Some of the papers in this special section also have companion abstract videos prepared by the authors of the papers. Interested readers can link to the videos through the TC portal page at http://www.computer.org/web/tc The paper “Non-Blocking Testing for Network-on-Chip” by Letian Huang, Junshi Wang, Masoumeh Ebrahimi, Masoud Daneshtalab, Xiaofan Zhang, Guangjun Li, and Axel Jantsch presents a method for the concurrent testing of multiple routers of a network-on-chip architecture in order to assess their status, that can be executed without blocking or dropping packets, thus not introducing performance penalties in the communications. The article “Capacitive and Inductive TSV-to-TSV Resilient Approaches for 3D ICs” by Ashkan Eghbal, Pooria M. Yaghini, Siavash Yazdi, Nader Bagherzadeh, and Michael Green discusses capacitive and inductive interaction among Through-Silicon Via wires of 3D integrated circuits. Two C. Bolchini is with the Dip. Elettronica, Informazione e Bioingegneria Politecnico di Milano, Piazza L. Da Vinci, 32 20133, Milan, Italy. S. Kundu is with 309J Knowles Engineering Bldg, University of Massachusetts, 151 Holdsworth Way, Amherst, MA 01003-9284. S. Pontarelli is with the Consorzio Nazionale Interuniversitario per le Telecomunicazioni, Via del Politecnico, 1 00133, Rome, Italy. E-mail: [email protected].